Data processors of increasing complexities are requiring a more thorough, efficient and less time-consuming approach to testing the various components within each data processor. Current methods of testing logic circuitry contained within a data processor include comprehensive functional testing, providing special test modes to read the contents of data registers, PLAs, ROMs, RAMs and other data storage elements incorporated within the data processor, and various data scanning techniques using data latches. Data scanning typically involves serially inputting a plurality of digital bits having predetermined logic values into a circuit being tested and detecting whether a predetermined digital output value is provided in response to the inputting of digital bits.
Typically, data scanning is limited to PLA circuitry or other repetitive, modular circuitry within a data processor. However, a need exists to be able to test most or all of the logic circuitry within a data processor from both a functional basis and a transistor fault basis. Testing is generally characterized as either functional testing or fault testing. A problem commonly associated with increasing the amount of logic circuitry which can be transistor fault tested by data scanning is an associated increase in circuitry required to perform the fault testing. Since an increase in circuit die size directly increases the cost of an integrated circuit, transistor fault test circuitry is typically considered to be a luxury which is not affordable in most applications. In addition, any circuitry which is added to perform functional and transistor fault testing may seriously impact speed performance of the logic circuitry being tested. As a result, test circuitry must not be inserted into any speed critical circuit paths.